The present invention relates to an electrically-erasable/programmable nonvolatile semiconductor memory device (EEPROM) in which data can be electrically rewritten and programmed data can be semipermanently stored.
An EEPROM in which data can be electrically erased/programmed generally uses a MOS transistor having a double gate structure of floating and control gate electrodes as its memory cell.
FIG. 1 shows an equivalent circuit diagram of a one-bit memory cell of such an EEPROM. This memory cell is constituted by data storage MOS transistor CT and selecting MOS transistor SG which is connected in series with transistor CT. A drain region and part of floating gate electrode FG of transistor CT overlap each other through an ultr thin silicon oxide film having a thickness of about 100 .ANG..
In a memory cell having such an arrangement, data programming is performed by injecting electrons from the drain region to the floating gate electrode of transistor CT through the ultra thin silicon oxide film by the Fowler-Nordheim tunnel effect. On the contrary, data erasure in this memory cell is performed by emitting electrons from the floating gate electrode to the drain region through the ultra thin silicon oxide film.
That is, injection of electrons is performed by setting the control gate electrode of transistor CT at a high potential, increasing a floating gate electrode potential by capacitive coupling between the control and floating gate electrodes, and causing the electrons to move from the drain region to the floating gate electrode through the ultra thin silicon oxide film by the tunnel effect.
On the other hand, the emission of electrons is performed as follows. That is, a high potential is applied to the drain region of transistor SG and its gate electrode is set at a high potential, so that the drain region of transistor CT outputs a high potential. In this state, the control gate electrode of transistor CT is set at a circuit ground potential (0 V), and the electrons are caused to move from the floating gate electrode to the drain region through the ultra thin silicon oxide film by the tunnel effect. Thus, electrons are emitted from the floating gate electrode.
In the conventional memory cell described above, an electron injection time can be reduced as the potential of the floating gate electrode is increased during the injection of electrons. In addition, an electron emission time can be reduced as the potential of the floating gate electrode is decreased during the emission of electrons.
In order to sufficiently increase or decrease the potential of the floating gate electrode so as to reduce the electron injection/emission time, a coupling capacitance between the floating and control gate electrodes must be increased as much as possible. In order to satisfy this requirement, it is important to increase an overlapping area of the floating and control gate electrodes.
FIGS. 2A and 2B show an example of an arrangement of a memory cell in which an overlapping area of floating and control gate electrodes can be made large while an area of each memory cel itself in a semiconductor chip is small and hence memory cells can be highly integrated. FIG. 2A is a plan view showing a pattern of this memory cell arrangement, and FIG. 2B is a sectional view taken along the line B-B* of FIG. 2A. Known examples corresponding to FIGS. 2A and 2B are Japanese Patent Disclosure (Kokai) Nos. 59-103366 and 59-205763.
In this memory cell arrangement, a source region of selecting MOS transistor SG and a drain region of data soorage MOS transistor CT are respectively formed by N.sup.+ -type regions 120 and 130 continuously formed in P-type semiconductor substrate 100. Ultra thin silicon oxide film 160 having a thickness of about 100 .ANG. is formed on part of region 130 to serve as a path of electrons. Polysilicon floating gate electrode 200 and polysilicon control gate electrode 230 are formed on channel region 190 and film 160 of transistor CT. Gate electrode 210 is formed on channel region 180 of transistor SG.
A drain region of transistor SG is represented by N.sup.+ -type region 110, and wiring for connecting a source region of transistor CT and source regions of transistors CT (not shown) in a plurality of other cells is represented by N.sup.+ -type region 150. In addition, silicon xxide films 170 sufficiently thicker (e.g., about 300- to 500-.ANG. thick) than film 160 are formed below electrodes 210 and 230.
In order to manufacture the above memory cell, region 130 is formed beforehand by implanting an N-type impurity in substrate 100 using a mask having an opening at region Z represented by an alternate long and dashed line in FIG. 2A. Thereafter, 100-.ANG. thick film 160 is formed on region 130, and film 170 having a thickness of several hundred .ANG. is formed on the other regions to be used as a gate oxide film. Subsequently, a first polysilicon layer to serve as electrode 200 and a second polysilicon layer to serve as electrode 230 are formed on transistor CT. A polysilicon layer to serve as electrode 210 is formed on transistor SG in the same step as that of the formation of electrode 230.
After formation of the above electrodes, an N-type impurity is implanted in substrate 100 using electrodes 210 and 230 as masks. As a result, regions 110 and 120 of transistor SG and region 150 of transistor CT are formed in self-alignment with electrodes 210 and 230, respectively. At this time, region 120 is connected to preformed region 130.
According to the above-mentioned steps for manufacturing the memory cell shown in FIGS. 2A and 2B, electrode 200 is not self-aligned with preformed region 130. That is, misalignment of electrode 200 with region 130 is caused during mask alignment for forming electrode 200.
Variations occur in a degree of capacitive coupling (i.e., a coupling capacitance) between region 130 and electrode 200 of transistor CT due to this mask misalignment. For example, assuming that region 130 is deviated upward and electrode 200 is deviated downward in FIG. 2A, the coupling capacitance is decreased. On the contrary, when region 130 is deviated downward and electrode 200 is deviated upward, the coupling capacitance is increased.
A value of coupling capacitance between region 130 of transistor CT and electrode 200 is important when region 130 is set at a high potential and electrons are emitted from electrode 200. This is because the potential of electrode 200 obtained when region 130 is set at a high potential depends on the value of coupling capacitance. A magnitude of coupling capacitance corresponds to an amount of electrons emitted from electrode 200, and variations in the amount of emitted electrons correspond to variations in a gate threshold voltage of transistor CT after emission of electrons.
In addition, in the memory cell shown in FIGS. 2A and 2B, region 150 of transistor CT is formed using electrode 230 as a mask. For this reason, mask misalignment between electrode 200 and region 130 causes variations in a channel length of transistor CT. Such a mask misalignment occurs in the same direction in a single semiconductor wafer. However, if a wafer is different, a direction of mask misalignment is different. Thus, the electrical characteristics of memory cell become different in each wafer.
In addition, when the above memory cells are arranged in a matrix manner to obtain an IC, region 110 of transistor SG and region 150 of transistor CT are generally used in common by memory cells adjacent to each other vertically (or laterally) on a plane of the memory cell pattern. For this reason, when the mask misalignment occurs between electrode 200 and region 130 as described above, a difference in electrical characteristics occurs between two memory cells adjacent to each other vertically (or laterally) in FIG. 2A.
Therefore, the memory cell shown in FIGS. 2A and 2B is not suitable for realizing an IC with small variations in the electrical characteristics.
Furthermore, when the memory cell shown in FIGS. 2A and 2B is manufactured, after region 130 is formed by ion-implantation and the like, ions implanted in region 130 are diffused in various heat treatment steps. When such a diffusion occurs, an effective length of the channel is substantially decreased, thereby raising a problem of variations in the electrical characteristics of the memory cells.
When the memory cell having the structure as shown in FIGS. 2A and 2B is used, an area of the memory cell per bit can be decreased, so that an IC with high packing density can be realized. On the contrary, because of this structure, mask misalignment as described above tends to occur during manufacture of an IC, thereby causing large variations in the electrical characteristics between memory cells.